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Freescale Semiconductor Advance Information
Document Number: MC34670 Rev. 3.0, 12/2006
IEEE 802.3af PD With Current Mode Switching Regulator
The 34670 combines a Power Interface Port for IEEE 802.3af Powered Devices (PD) and a high performance current mode switching regulator. It allows a designer to build PDs with a minimum of external components by means of integrating the required IEEE 802.3af functions and all functions necessary to build a high efficiency DC/DC converter. On the PD side the 34670 fully supports the IEEE802.3af standard and provides complete signature and power classification functions. It controls inrush current limiting and incorporates adjustable undervoltage lockout. The switching regulator provides excellent line and load regulation. It drives an external Power MOSFET with sense resistor. Features * * * * * * * * * * * * * Integrated IEEE 802.3af Compliant Interface Signature Detection and Classification Functionality Integrated Isolation Switch Programmable Inrush Current Limiting Control Adjustable Undervoltage Lockout Input Voltage Range up to 80 V Current Mode Control Adjustable Oscillator Leading Edge Blanking Internal Slope Compensation Circuitry Input Overvoltage Protection 50% Duty Cycle Limitation Pb-Free Packaging Designated by Suffix Code EG
34670
POWER OVER ETHERNET
EG SUFFIX (PB-FREE) 98ASB42343B 20-PIN SOICW
ORDERING INFORMATION
Device MCZ34670EG/R2 Temperature Range (TA) -40C to 85C Package 20 SOICW
PSE HUB OR SWITCH
TX PHY RX
RJ-45
ETHERNET APPLIANCE (PD)
RX PHY TX
HOST PROCESSOR
PSE POWER CONTROLLER SWITCH -48V GND -48V CAT 5 CABLE PD POWER CONTROLLER ISOLATION SWITCH
HOST CONTROLLER
48 V POWER SUPPLY
34670
DC/DC
Figure 1. 34670 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
FREQ
HIGH VOLTAGE REGULATOR 2.5V 8V 0.8R R INTERNAL SUPPLY POR EN UNDERVOLTAGE UV or UVLO LOCKOUT OVERVOLTAGE DETECTION CONTROL LOGIC UV or UVLO 5A
+
VPWR
VDD
5.7V SR OSC R Q 3.5V
RCLA
GATE
SS
0.3V 4.5V 5k PWM COMPARATOR 0.6 - 2.6V BLANK 0.4V 1.4V 0.6V R S Q
CS
ILIM UVLO
+
CURRENT LIMITATION
3 GATE DRIVE TEMP SENSOR SLOPE COMP
+
COMP FB
1.2V REG DETECT
250mV
RSENSE
VIN RESET
VOUT
Figure 2. 34670 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
VPWR VPWR RCLA UVLO TEST1 TEST2 FREQ ILIM VIN VIN
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD GATE CS FB COMP SS RESET VOUT VOUT VOUT
Figure 3. 34670 Pin Connections Table 1. 34670 Pin Definitions
Pin Number 1, 2 3 4 5 6 7 8 9 10 11, 12 13 14 15 16 17 18 19 20 Pin Name VPWR RCLA UVLO TEST1 TEST2 FREQ ILIM VIN VIN VOUT VOUT RESET SS COMP FB CS GATE VDD Output Voltage Output Voltage RESET Output (active low) Soft Start Input Compensation Pin Feedback Input Current Sense Gate Driver Output VDD Output This pin is the drain of the internal Power MOSFET (high current path). This pin is the drain of the internal Power MOSFET (low current path). This is an active-low RESET output signal. This pin is referenced to VOUT. Connect an external capacitor to SS. The internal current source charges the capacitor and generates a soft-start ramp. COMP is the output of the error amplifier and is available for feedback compensation. COMP is pulled-up by an internal 5.0 k resistor to 5.0 V. This is the inverting input of the error amplifier. In non-isolated applications it's connected to the secondary output through a resistor divider. The current sense pin CS senses a voltage that is proportional to the current through the sense resistor. GATE drives the gate of the external power MOSFET. GATE sources and sinks up to 1.0 A. VDD mainly supplies the gate of the external power MOSFET. Connect a capacitor from VDD to VOUT. Frequency Adjustment Inrush Current Limit Negative Supply Voltage Adjusts the internal oscillator frequency by connecting a resistor between FREQ and VIN. Used to adjust the inrush current limit of the isolation switch, add a resistor between ILIM and VIN. This is the most negative power supply input. Formal Name Positive Supply Voltage Input Classification Resistor Undervoltage Lookout Test pins Definition This is the most positive power supply input. The load connects between this pin and the VOUT pin. Connect a resistor between RCLA and VIN to select the class of the PD. Used to adjust the undervoltage lookout threshold voltage, connected to VIN to use the default threshold voltage. Connect to VIN in application mode.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to VIN unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Power Supply Voltage Supply Current VOUT Pins Voltage UVLO Voltage RCLA Voltage ILIM Voltage FREQ Voltage VPWR IPWR VOUT VUVLO VRCLA VILIM VFREQ -0.3 to 80 18 -0.3 to (VPWR + 0.3) -0.3 to 10 -0.3 to 5.0 -0.3 to 5.0 -0.3 to 5.0 With respect to: VOUT(2) FB, COMP Voltage
SS Voltage
Symbol
Value
Unit
V mA V V V V V
VIN(3) -0.3 to 80 -0.3 to 80 -0.3 to 80 -0.3 to 80 -0.3 to 80 -0.3 to 80 V 2000 200 V V V V V
VFB, VCOMP VSS VDD VGATE VCS VRESET VESD1 VESD2 ECL
-0.3 to 5.0 -0.3 to 5.0 -0.3 to 16 -0.3 to (VDD + 0.3) -0.3 to 5.0 -0.3 to 15
VDD Voltage GATE Voltage CS Voltage RESET Voltage ESD Voltage
(1)
Human Body Model Machine Model Output Clamp Energy
12
mJ
NotesNotes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 2. 3. Measured value relative to VOUT Measured value relative to VIN
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 2. Maximum Ratings (continued) All voltages are with respect to VIN unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings THERMAL RATINGS Operating Temperature Ambient
(4)
Symbol
Value
Unit
C
TA
TJ TSTG
(7)
-40 to 85 120 -65 to 150 800 103 47 Note 6 180 150 C C C C mW C/W
Junction (8), (9) Storage Temperature Power Dissipation (TA = 25 C) Thermal Resistance Junction to Ambient 20LD SOIC W/B Package (9) Peak Package Reflow Temperature During Reflow (5), (6) Thermal Shutdown Temperature Thermal Shutdown Recovery Temperature
PD RJA RJB TPPRT TSHUT THYST
NotesNotes 4. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking. 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 6. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 7. Maximum power dissipation at indicated ambient temperature in free air with no heatsink used. 8. For TA = 85C and PD = 700 mW and RJB = 47C/W. 9. Measured with 4 layers 2s2p JEDEC std. PCB.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 30 V VPWR 60 V, - 40C TA 85C, VIN = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SIGNATURE DETECTION Input Offset Current (1.4 V VPORT 9.5 V) Differential Input Resistance (1.4 V VPORT 9.5 V) CLASSIFICATION Classification Current (13.5 V VPORT 20 V) Class 0: RCLASS = 4.42 k Class 1: RCLASS = 475 Class 2: RCLASS = 261 Class 3: RCLASS = 169 Class 4: RCLASS = 113 Classification Current Limit RCLA Reference Voltage (13.5 V VPORT 20 V) INRUSH CURRENT LIMITATION (37 V VPORT 60 V) (RLIM) Input Inrush Current, ILIM connected to VIN Input Inrush Current, ILIM connected via resistor RILIM to VIN RILIM = 12.1 k RILIM = 42.2 k RILIM = 191 k NORMAL OPERATION (VPWR, UVLO) Supply Voltage Supply Current
(10)
Symbol
Min
Typ
Max
Unit
IOFFSET RDIFF
-- 600
-- --
10 --
A k
ICLASS 0 9.0 17 26 36 ICLASS(LIM) VRCLA -- 4.0 -- -- -- -- -- -- 4.5 4.0 12 20 30 44 50 5.0
mA
mA V
IINRUSH IINRUSH
--
--
350
mA
130 70 30
180 110 65
250 165 100
VPWR IPWR VUVLO(ON) VUVLO(OFF) VHYST(INT) VUVLO(PR) VUVLO(REF) VHYST(EXT) IUVLO(B)
-- -- -- 30 6.0 25 1.96 -- --
-- 4.5 -- -- -- -- 2.0 15 --
60 7.3 40 -- -- 50 2.04 -- 1.0
V mA V V V V V % A
Default Turn-On Voltage (UVLO = VIN) Default Turn-Off Voltage (UVLO = VIN) UVLO Hysteresis when set internally External UVLO Programming Range UVLO Reference Voltage UVLO Hysteresis when set externally UVLO Bias Current ISOLATION SWITCH (ILIM) On-Resistance (VPORT = 48 V, IPORT = 350 mA) (11) Isolation Switch Current Limit in Normal Operation Mode Notes 10. GATE pin open, PWM controller running. 11. Measured across VIN and VOUT.
RDS(ON) ILIM
-- 380
-- --
500 700
m mA
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics(continued) Characteristics noted under conditions 30 V VPWR 60 V, - 40C TA 85C, VIN = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic PWM COMPARATOR (COMP) COMP Control Voltage Range COMP Input Bias Current HIGH VOLTAGE REGULATOR Regulator Output Voltage Regulator Turn-Off Voltage
(12)
Symbol
Min
Typ
Max
Unit
VCOMP ICOMP(B)
1.3 --
-- --
4.0 1.8
V mA
VDDREG VREG(OFF) IREGLIM IREGDC
8.0
9.0 VDDReg +0.5
10 -- 15 5.0
V V mA mA
Regulator Current Limitation (13) Regulator Continuous Current GATE DRIVER (UVLO) Gate Driver UVLO, Rising Gate Driver UVLO, Falling CURRENT LIMIT (CS) CS Threshold Voltage CS Bias Current ERROR AMPLIFIER Reference Voltage OVERVOLTAGE SHUTDOWN OVLO Threshold, Rising OVLO Threshold, Falling OVLO Hysteresis SOFT-START (SS) SS Output Voltage SS Source Current SS Sink Current Shutdown Threshold Voltages
7.0 --
-- --
VGATE(R) VGATE(F)
VDD-0.5 --
-- --
-- 6.5
V V
VCS ICS(B)
320 --
400 --
480 30
mV A
VREF
1.164
1.2
1.236
V
VOV(R) VOV(F) VOV(HYS)
66 63 --
-- -- 3.0
72 69 --
V V V
VSS ISS(OUT) ISS(IN) VSS(R) VSS(F)
-- 3.25 -- 0.48 0.24
2.0 5.0 2.0 0.6 0.3
-- 6.75 2.25 0.72 0.40
V A mA V
THERMAL SHUTDOWN Thermal Shutdown Temperature Thermal Hysteresis Notes 12. An external voltage has to be applied. 13. Thermal limitations of the device might derate usable current range. TSHUTDOWN THYS 150 -- 165 30 180 -- C C
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 30 V VPWR 60 V, - 40C TA 85C, VIN = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic NORMAL OPERATION Turn-On Filter Time Turn-Off Filter Time PWM COMPARATOR Slope Compensation Ramp as a Function of Switching Frequency fPWM = 100 kHz fPWM = 250 kHz fPWM = 400 kHz Duty Cycle Limit (14) GATE DRIVER Rise Time (10% - 90%), CLoad = 2.0 nF, VDDREG = 9.0 V Fall Time (90% - 10%), CLoad = 2.0 nF, VDDREG = 9.0 V CURRENT LIMIT Blanking Time (14) PWM OSCILLATOR Default Clock Frequency (FREQ connected to VIN) Oscillator Frequency Adjusting Resistor Range Oscillator Frequency Range, RFREQ = 121 k Oscillator Frequency Range, RFREQ = 499 k ERROR AMPLIFIER Gain Bandwidth (14) DC Open Loop Gain RESET OUTPUT RESET Output Low Voltage (IRESET, SINK = 20 mA) RESET Output Filter Time Notes 14. Guaranteed by design. Not production tested. VRESET,LOW tRESET -- -- -- 20 0.8 -- V s GBW AVOL 1.0 -- -- 80 -- -- MHz dB fPWM RFREQ fRANGE fRANGE 175 121 320 80 225 -- -- -- 325 499 480 120 kHz k kHz kHz tBLANK 40 50 60 ns tR tF -- -- -- -- 50 30 ns ns m100 m250 m400 DMAX -- -- -- -- 10 25 40 -- -- -- -- 48 % mV/s tFILT(ON) tFILT(OFF) -- -- 200 200 -- -- s s Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS TYPICAL SWITCHING WAVEFORMS
TYPICAL SWITCHING WAVEFORMS
w/o snubber
w/ snubber w/ snubber w/o snubber
Figure 4. Drain Voltage of Switching MOSFET
Figure 6. Secondary Voltage before Diode
Figure 5. Secondary and Output Voltage
Figure 7. Gate Voltage and Voltage at CS pin
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
MC34670 Efficiency Plot: Vo = 5V, w/o bias winding, Coilcraft DA2142-AL 90.00 85.00 80.00 75.00 % 70.00 65.00 60.00 55.00 50.00 0.40 0.60 0.80 1.00 1.20 I O [A] 1.40 1.60 1.80 2.00 57V 48V 36V
MC34670 Efficiency Plot: Vo = 5V, w/ bias winding, Coilcraft DA2362-AL 90.00 85.00 80.00 75.00 % 70.00 65.00 60.00 55.00 50.00 0.40 0.60 0.80 1.00 1.20 I O [A] 1.40 1.60 1.80 2.00 57V 48V 36V
Figure 8. Efficiency Plot
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 34670 combines a Power Interface Port for IEEE 802.3af Powered Devices (PD) and a high performance current mode switching regulator. It allows a designer to build PDs with a minimum of external components by means of integrating the required IEEE 802.3af functions and all functions necessary to build a high efficiency DC/DC converter. Thus 34670 gives the system designer a device that drastically reduces cost and board space. On the PD side the 34670 fully supports the IEEE802.3af standard and provides complete signature detection and power classification functions. It controls inrush current limiting and incorporates an adjustable undervoltage lockout. The 34670 includes thermal protection circuitry to protect the device in case of high power dissipation. The 34670 also offers an input overvoltage detection to protect the external switching MOSFET by disabling the gate driver in case of input line overvoltage. The switching regulator provides excellent line and load regulation. It drives an external power MOSFET with sense resistor. The switching frequency is adjustable between 100 kHz and 400 kHz. The output voltage feedback information can be accomplished by an optocoupler, if isolation is required. An internal logic control block manages the sequencing of signature detection, classification and proper turn on and turn off of the DC/DC converter.
FUNCTIONAL PIN DESCRIPTION POSITIVE SUPPLY VOLTAGE INPUT (VPWR)
This is the most positive power supply input. The load connects between this pin and the VOUT pin.
RESET OUTPUT (RESET)
This is an active-low RESET output signal. This pin is referenced to VOUT.
CLASSIFICATION RESISTOR (RCLA)
Connect a resistor between RCLA and VIN to select the class of the PD.
SOFT START INPUT (SS)
Connect an external capacitor to SS. The internal current source charges the capacitor and generates a soft-start ramp.
UNDERVOLTAGE LOOKOUT (UVLO)
Used to adjust the undervoltage lookout threshold voltage, connected to VIN to use the default threshold voltage.
COMPENSATION PIN (COMP)
COMP is the output of the error amplifier and is available for feedback compensation. COMP is pulled-up by an internal 5.0 k resistor to 5.0 V.
TEST PINS (TEST1, TEST2)
Connect to VIN in application mode.
FEEDBACK INPUT (FB)
This is the inverting input of the error amplifier. In nonisolated applications it's connected to the secondary output through a resistor divider.
FREQUENCY ADJUSTMENT (FREQ)
Adjusts the internal oscillator frequency by connecting a resistor between FREQ and VIN.
INRUSH CURRENT LIMIT (ILIM)
Used to adjust the inrush current limit of the isolation switch, add a resistor between ILIM and VIN.
CURRENT SENSE (CS)
The current sense pin CS senses a voltage that is proportional to the current through the sense resistor.
NEGATIVE SUPPLY VOLTAGE (VIN)
This is the most negative power supply input.
GATE DRIVER OUTPUT (GATE)
GATE drives the gate of the external power MOSFET. GATE sources and sinks up to 1.0 A.
OUTPUT VOLTAGE (VOUT)
This pin is the drain of the internal Power MOSFET (high current path and low current path).
VDD OUTPUT (VDD)
VDD mainly supplies the gate of the external power MOSFET. Connect a capacitor from VDD to VOUT.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES POWER DEVICES (PD) INTERFACE
The PD interface of the 34670 has been designed to comply with the requirements of the IEEE standard 802.3af. The device operates in three different modes, depending on the input voltage.
I
PD OPERATING MODES
The IEEE 802.3af standard defines three operating modes in general. These modes are summarized in Table 5. Table 5. PD Operating Modes
Operating Mode Signature Resistor Detection Classification Normal Operation Mode Voltage at PD Input Connector 2.7 V - 10.1 V 14.5 V - 20.5 V 37 V - 57 V
I2 I1
SIGNATURE RESISTOR DETECTION
A PD shall present a valid detection signature at the PD input connector to get properly detected as a power over LAN enabled pin. Valid and non-valid detection signature regions are separated by guard bands. See Figure 9 for valid and non-valid signature regions.
valid region
V1
2 1 dR = -------------------I2 - I1 V -V
V2
V
Figure 10. dR Measurement It can be seen in Figure 11, that a signature resistor of 25 k as defined in IEEE 802.3af and two diodes in series would lead to an effective resistance out of the valid region specified in Figure 9. At low voltages the effective resistance is above the maximum allowed value of 26.25 k, as illustrated in Figure 11. Therefore one has to adjust the signature resistor RSIG (R1 and R2, see UVLO Adjustment on page 13) to a value below 25 k to stay within the valid region.
non-valid region
non-valid region
Signature [k] 12 23.75 26.25 45
Figure 9. Signature Resistance Guard Bands The effective resistance across the input pins is calculated by two subsequent voltage-current measurements made during the detection process by the PSE.
VALID PD DETECTION SIGNATURE CHARACTERISTICS
During signature detection phase the Power Sourcing Equipment (PSE) applies a voltage in the range 2.7 V 10.1 V on the PI connector and looks for the 25 k signature resistor. Since the PD circuitry includes bridge rectifiers, the PD has to compensate for the voltage drop across the diodes and the diodes serial resistance. The effective signature resistance dR is obtained by the V-I-Slope measurement of the PSE (Figure 10). Figure 11. dR at Low Input Voltages
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
CLASSIFICATION
A PD may optionally be classified by the PSE. The intent of classification is to provide a method for more efficient power allocation through the PSE. The PD classification allows the PSE to identify four different (power) classes depending on the required power that the PD will draw during normal operation. The classes and the corresponding maximum power drawn by the PD is shown in Table 6. Table 6. PD Classes
Class 0 1 2 3 4 Usage Default Optional Optional Optional Reserved Maximum Power [W] 0.44 - 12.95 0.44 - 3.84 3.84 - 6.49 6.49 - 12.95
CLASSIFICATION SIGNATURE LOAD CURRENT
The implementation for the classification circuitry is shown in Figure 12.
+VPORT
34670
VPWR + EN
Vref
RCLA ICLASS VIN
RCLASS
-VPORT
--
PD CLASSES
During classification probing by the PSE, the PD applies the appropriate load current onto the line. The PSE measures the load current and can determine the classification as described in Table 7.
.
Figure 12. Classification Circuitry A constant voltage is applied at pin RCLA and depending on the resistor RCLASS, a current from +VPORT to -VPORT is flowing with the following relation: V RCLA I CLASS = -------------------R CLASS ICLASS is the classification current that is measured by the PSE. The values for the RCLASS resistor corresponding to the appropriate class are listed in Table 8. Table 8. PD Class vs. Classification Resistor RCLASS
Class 0 1 2 3 4 Classification Current [mA] 2.0 10.5 18.5 28 40 RCLASS [] 4.42k 475 261 169 113
Table 7. PD Class vs. Classification Current
Classification Current [mA] Class Min 0 1 2 3 4 0 9 17 26 36 Max 4 12 20 30 44 14.5 - 20.5 Volts measured at PD input connector Condition
UVLO ADJUSTMENT
The 34670 has default UVLO settings that corresponds to the IEEE 802.3af standard. Nevertheless the user can adjust the UVLO by an external resistor divider as sketched in Figure 13. Since the UVLO resistor divider replaces the
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
signature resistor, the total resistance of R1+R2 must equal 25 k.
+VPORT VPWR
R 1 = R SIG - R 2
V UVLO ( OFF ) = V UVLO ( ON ) 0.85 The typical turn-off voltage VUVLO(OFF) is 85% of the turn on voltage VUVLO(ON).
RCLA
INRUSH CURRENT LIMITATION
The 34670 has been designed to interface also with legacy PoE-PSEs which do not meet the inrush current requirement of the IEEE 802.3af specification. By setting the initial inrush current limit to a low level, a PD using the 34670 minimizes the current drawn from the PSE during start-up. The maximum inrush current level can be set by connecting a resistor from ILIM to VIN as illustrated in Figure 15.
+VPORT VPWR RCLASS RCLA
R1 UVLO R2 ILIM VIN -VPORT
Figure 13. UVLO Adjustment by External Resistor Divider To use the default settings for UVLO, the pin UVLO must be connected to VIN. In this case, a valid signature resistor has to be placed between -VPORT and +VPORT. This configuration can be seen in Figure 14.
+VPORT
RSIG 25k UVLO RILIM
VPWR
ILIM VIN
RCLA
-VPORT
RSIG 25k UVLO ILIM VIN -VPORT
Figure 15. Inrush Current Limitation by External Resistor RILIM The following table shows the selectable current limits and the corresponding resistor value that has to be connected between pins ILIM and VIN: Table 9. Inrush Current Limit vs. RILIM
Inrush Current Limit [mA] 180 110 65 RILIM Value [k] 12.1 42.2 191
Figure 14. Default UVLO Settings To calculate the values for R1 and R2 the following equations should be used:
R 1 + R 2 = R SIG
UVLO ( REF ) R 2 = --------------------------------- R SIG
V
V UVLO ( ON )
where VUVLO(ON) is the desired turn-on voltage threshold and VUVLO(ref) the UVLO reference voltage.
After powering up, the 34670 switches to the high level current limit, thereby allowing the PD to consume up to 12.95 W if a 802.3af PSE is present.
PULSE WITH MODULATOR CONTROLLER CURRENT-MODE CONTROL OPERATION
The 34670 offers current-mode control operation with leading-edge blanking. The current-limit comparator monitors the CS pin at all times and provides cycle-by-cycle current limit. The CS signal contains a leading-edge spike that is the result of the MOSFET gate charge current, capacitive and diode reverse recovery current of the power circuit. The leading-edge blanking of the CS signal prevents the PWM comparator from premature termination of the on cycle. The 34670 limits the duty cycle to 50%. This is advantageous for applications which are not allowed to exceed an on-time of 50 % of the switching period TS. Beside the duty-cycle limit, slope compensation is provided to stabilize the inner current loop and avoid oscillations for
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
converters running in continuos conduction mode (CCM). The value of the slope compensation depends on the switching frequency. See Table 10. Table 10. Slope Compensation Values
Switching Frequency [kHz] 100 250 400 Slope Compensation [mV/s] 10 25 50
NP
T1 NS
RV
ISOLATED OPTOCOUPLER FEEDBACK
Isolated voltage feedback can be accomplished by using an optocoupler and a shunt regulator (see Figure 19). The output voltage accuracy is a function of the accuracy of the shunt regulator and feedback resistor divider tolerance, therefore the feedback resistors should have an appropriate accuracy. Since the error amplifier function is implemented on the secondary side by the optocoupler and a 3-pin adjustable shunt regulator, the internal error amplifier of the 34670 is not used. The FB pin is connected to VOUT, thus disabling the internal open-drain error amplifier. The bias voltage for the optocoupler is accomplished through the internal 5.0 k pull-up resistor between COMP and an internal 5.0 V reference. When a TL431 or TLV431 shunt regulator is used for output voltage regulation, the output voltage is set by the ratio of resistors R1 and R2, see Figure 16 for details. The output voltage is given by the following equation:
R 1 V O = V REF 1 + ------- R 2
TLV431
R1
R2
Figure 16. Isolated Optocoupler Feedback
ISOLATED PRIMARY CONTROL FEEDBACK
Another option to accomplish isolated feedback is the use of a tertiary winding (see Figure 21). The advantage of this solution without optocoupler and shunt regulator is clearly the cost effectiveness. Nevertheless the line and load regulation is worse than with optocoupler feedback. When isolated primary feedback is used, the loop compensation components are connected between pins COMP and FB.
where VREF = 1.24 V for the TLV431 (VREF = 2.5 V for the TL431).
INTERNAL REGULATORS
The internal high voltage regulator of the 34670 regulates from the input voltage across VPWR and VIN down to the VDD voltage. During start-up the high voltage regulator provides the necessary voltage for the internal gate driver to commence switching. If the external MOSFET gate drive pulls less than 3.0 mA under all circumstances, an auxiliary transformer winding that usually provides the bias voltage for the chip and the gate driver is not required. In cases where the external MOSFET gate drive pulls more than 5.0 mA, an auxiliary winding is needed to reduce the power dissipation in the internal high voltage LDO. See Figure 18 for an application drawing. It is recommended to add a 0.1 F ceramic capacitor in parallel with the existing load capacitor. This reduces noise at the VDD pin caused by the auxiliary winding. The high voltage regulator is disabled when the VDD pin is forced by an external voltage above the VDD regulation point.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
This reduces power dissipation in the device and improves overall efficiency.
VDD
12
VREG(OFF) VGATE(R)
10 8
When the overvoltage protection is triggered (VPWR > VOV(R)), the gate driver is immediately disabled. At the same time, the slow discharge of CSS is initiated. While the soft-start capacitor is discharging, the gate driver remains disabled. Once VSS = 0.3 V and the overvoltage (VPWR < VOV(F)) condition disappears, operation resumes through a regular soft-start.
CURRENT-SENSE COMPARATOR
The current-sense (CS) comparators and its associated circuitry limits the peak current through the MOSFET. Current is sensed at CS pin as a voltage across the sense resistor RCS between the source of the MOSFET and VOUT. The CS input has two voltage trip levels, a 600mV high limit and a 400 mV low limit. When the voltage on CS produced by a current through the current sense resistor exceeds the high limit threshold, the current ON-cycle is immediately terminated and the GATE output is pulled low. If the low limit threshold is exceeded for longer than 50 ns (typical blanking time), the current ON-cycle is also terminated. The blanking time ensures a false termination of the switching cycle caused by the leading-edge spike on the sense waveform. The current-sense resistor RCS is selected according to the following equation:
400mV R CS = ---------------------------------------I LIM ( primary )
VGATE(F)
6 4 2
t GATE enable HVReg enable
Figure 17. VDD and MOSFET Driver Output Behavior A load capacitor connected to VDD ensures a proper filtering of the VDD voltage. The minimum capacitance value for this load capacitor should be at least 10 F. An electrolytic type capacitor is sufficient. Please refer to application note A/N3279 for further information about the size of the capacitor. If VDD falls below the UVLO threshold, the voltage regulator is disabled and the MOSFET driver output (GATE) is held low.
where ILIM(primary) is the maximum peak primary-side
current. In case of an overcurrent in the external MOSFET the current switching cycle is terminated and GATE is pulled low. The soft-start capacitor CSS is discharged and after removal of the faulty condition the PWM is re-started through a regular soft start.
PWM CONTROLLER UVLO, SOFT-START, AND SHUTDOWN FUNCTION
The soft-start function provided by the 34670 allows the output voltage to ramp up in a controlled way, thus eliminating output voltage overshoot. While the PWM controller is in undervoltage lockout, the capacitor CSS connected to the SS pin is fully discharged. After coming out of undervoltage lockout, an internal current source starts charging the capacitor CSS to initiate soft-start. When VSS has reached 0.6 V, the gate driver is enabled and PWM operation begins. The duty cycle during soft-start is primarily controlled by the internal sawtooth voltage and the voltage at the SS pin. If the voltage at the SS pin is above 2.6 V, the regular PWM control through pins CS, COMP, and FB takes over and soft-start is finished. The following equation calculates the total soft-start time:
t SS [ ms ] = 0.4 C SS [ nF ]
PWM OSCILLATOR
A default 250 kHz oscillator sets the switching frequency of the PWM controller. The frequency of the oscillator can be adjusted between 100 kHz and 400 kHz by an optional external resistor RFREQ connected from the FREQ pin of the integrated circuit to VIN. The appropriate switching frequency fPWM can be calculated as shown below:
47920 f PWM [ kHz ] = ----------------------------------- + 4 R FREQ [ k ]
where fPWM is the PWM switching frequency and RFREQ is the frequency adjusting resistor. To use the default frequency of 250 kHz the FREQ pin can be connected to VIN or can be left open.
OVERVOLTAGE SHUTDOWN
The 34670 includes an overvoltage protection (OVP) feature that turns off the external MOSFET when the input voltage exceeds the overvoltage threshold.
RESET OUTPUT
The RESET pin is an open drain output. The reset control circuit supervises the FB voltage and recognizes if the output
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
voltage is out of regulation. In this case the RESET pin is pulled low. The RESET output can only be used in non-isolated applications. There is a 20 s delay filter preventing erroneous RESET output pulses. During soft-start, RESET is held low. RESET is released when the PWM controller is in regulation.
N-CHANNEL MOSFET GATE DRIVER
GATE drives an N-channel MOSFET. GATE sources and sinks large transient currents up to 1.0 A to charge and discharge the MOSFET gate. The GATE output is supplied by the internal generated VDD voltage, which is internally set to approximately 9.0 V. For Power-over-Ethernet applications, the used MOSFET must be able to withstand a DC level of ~60 V plus the reflected voltage at the primary side of the transformer. This requires a MOSFET rated at 150 V or 200 V.
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Please refer to application note AN3279 for further information of PD design and layout recommendations.
T1 NAUX VOUT = 5V@2A 3 RX 6 1 TX 2 CIN 4 5 -VPORT CSS 7 8 RCLASS R2 R1 UVLO ILIM VIN SS FREQ COMP FB VOUT VPWR RESET RCLA VDD M1 GATE CS RCS CDD 0.1 F CPORT RV
+VPORT
34670
NP
NS
Figure 18. Isolated Flyback Converter with Bias Winding
+VPORT T1 3 RX RX
6 RX + 1 TX +
VOUT = 5V@2A D1
34670
VPWR RESET VPORT RCLA VDD R1 CIN 4 5 SPARE+ -VPORT 7 8 SPARECSS RCLASS R2 UVLO ILIM VIN SS FREQ COMP FB VOUT M1 GATE CS RCS CDD CPORT
NP
NS
TX
2 TX
RV
Figure 19. Isolated Flyback Converter without Bias Winding
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TYPICAL APPLICATIONS
T1 +VPORT NR
3 RX 6 1 TX 2 CIN 4 5 -VPORT CSS 7 8 RCLASS R2 R1 UVLO ILIM VIN SS FREQ COMP FB VOUT Rv2 VPWR RESET RCLA VDD M1 GATE CS RCS Rv1 CDD CPORT RV
34670
NP
NS
Figure 20. Isolated Forward Converter
T1 CAUX +VPORT NAUX VOUT = 5V@2A 3 RX 6 1 TX 2 CIN 4 5 -VPORT CSS 7 8 C1 C2 R2 RCLASS R2 R1 UVLO ILIM VIN SS FREQ COMP FB VOUT VPWR RESET RCLA VDD M1 GATE CS RCS CDD CPORT
34670
NP
NS
Figure 21. Isolated Flyback with Primary Control
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TYPICAL APPLICATIONS
+VPORT T1 3 RX 6 1 TX 2 CIN 4 5 -VPORT CSS 7 8 C1 C2 R2 Rb RCLASS R4 R3 UVLO ILIM VIN SS FREQ COMP FB VOUT VPWR RESET RCLA VDD M1 GATE CS RCS CDD CPORT NP VOUT = 5V@2A D1
34670
NS
CO
R1
Figure 22. Non-Isolated Flyback Converter
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REFERENCE DOCUMENTS
REFERENCE DOCUMENTS
Table 11. Reference Documents
Title IEEE Std 802.3afTM-2003 MC34670 Usage and Configuration LIterature Order Number IEEE Std 802.3afTM-2003 AN3279 Publication Date 18 June 2003
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
EG SUFFIX (PB-FREE) 20-PIN PLASTIC PACKAGE 98ASB42343B ISSUE J
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REVISION HISTORY
REVISION HISTORY
Revision 1.0 2.0
Date 8/2006 9/2006
Description of Changes
* Initial release * Change to UVLO Hysteresis when set internally on page 6, Regulator Current Limitation (13) on page 7, OVLO Threshold, Rising on page 7, OVLO Threshold, Falling on page 7, Shutdown Threshold Voltages on page 7, and Default Clock Frequency (FREQ connected to VIN) on page 8 * Changed Data Sheet category to "Advanced Information*" * Typ and Max change to RCLA Reference Voltage (13.5 V VPORT 20 V) on page 6 * Deleted Oscillator Frequency Adjusting Resistor Range in Static Electrical Characteristics * Split Oscillator Frequent Range into two parameters, Oscillator Frequency Range, RFREQ = 121 k on page 8 and Oscillator Frequency Range, RFREQ = 499 k on page 8 * Added note to Duty Cycle Limit (14) on page 8, Blanking Time (14) on page 8, and Gain Bandwidth (14) on page 8 * Changed nomenclature for Peak Package Reflow Temperature During Reflow (5), (6) on page 5 * Changed name and value for Thermal Shutdown Recovery Temperature on page 5
3.0
12/2006
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MC34670 Rev. 3.0 12/2006

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